Date of Award

2026-05-01

Degree Name

Master of Science

Department

Computer Science

Advisor(s)

Christoph Q. Lauter

Second Advisor

Martin Kumm

Abstract

This thesis explores the design of synchronization mechanisms that allow multiple FPGA boards to operate as if they were a single coherent timing domain. The solutions span three layers: a software PLL for E1 telecommunication links, a PCIe-based timestamp exchange protocol, and a hardware-level multi-FPGA mesh architecture. Across these layers, the work demonstrates that practical, low-cost synchronization can achieve sub-microsecond accuracy without the burden of specialized hardware such as GPSDOs or White Rabbit infrastructure. Experiments show stable alignment within the nanosecond-microsecond range, validating the feasibility of the proposed methods for SDR and telecom applications.

Language

en

Provenance

Received from ProQuest

File Size

94 p.

File Format

application/pdf

Rights Holder

Christina Alicia Alejandra Carreon Jimenez

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