Dynamic pipeline network optimization
Abstract
This dissertation presents a new algorithm for dynamic pipeline network time-area optimization, called the Skipping-SAGA. It is a combination of the skipping, genetic, and simulated annealing algorithms. The skipping algorithm finds data flow bottlenecks in pipeline network designs and replicates the components that are responsible for these bottlenecks in order to produce an optimum time-area design. Subsequently, the genetic and simulated annealing algorithms are used to optimize the chip layout. The skipping-SAGA produces an optimal solution in terms of the lowest cost and the highest performance under certain constraints. Specifically, it produces a minimum of AαT for chip area, A, and execution time, T, where α is a nonnegative number. The results of the skipping-SAGA algorithm were compared with published results of experiments conducted on the MCNC benchmarks using simulated annealing, dynamic weighting Monte Carlo (DWMC), relaxed simulated tempering and the commercial version of TimberWolf 1.3.3 software. The results indicate that the skipping-SAGA algorithm improved the circuit layout area by an average of 3% over the other algorithms, including the TimberWolf application. As a part of this research, the skipping-SAGA software, based on the skipping-SAGA algorithm, was developed. The software offers a fast method of optimization that is capable of handling a large number of circuits on one chip.
Subject Area
Electrical engineering|Computer science|Mathematics
Recommended Citation
Alawneh, Yahya Zakaria, "Dynamic pipeline network optimization" (2002). ETD Collection for University of Texas, El Paso. AAI3080477.
https://scholarworks.utep.edu/dissertations/AAI3080477