Radiation-hardened analog circuits in partially-depleted SOI CMOS
Abstract
The traditional use of SOI CMOS has been in the development of radiation-hardened integrated circuits for the military and aerospace. In this thesis, the possibility of implementing SOI analog circuits where body ties are used selectively to reduce a circuit's total area is studied. Based on a 0.18um adaptation of the PD BSIMSOI2.0 transistor model, a simple two-stage op amp was simulated in SPICE3f5 to analyze the effects on performance (e.g. gain, 3db and unity-gain frequencies, phase margin) of having specific blocks in the architecture operating with floating bodies. From simulation results, optimal op amp performance was only obtained when all transistors included a body tie—NFETs to VSS, PFETs to VDD—; however, minimal performance degradation occurs in the case when only the biasing network in the circuit is untied. Simulation of radiation-effects on SOI op amp performance is also addressed in this investigation. This research is preliminary to the pursuit of radiation-hardened, reconfigurable analog SOI hardware development by our group in the near future. (Abstract shortened by UMI.)
Subject Area
Electrical engineering
Recommended Citation
Perez, Alfredo, "Radiation-hardened analog circuits in partially-depleted SOI CMOS" (2005). ETD Collection for University of Texas, El Paso. AAI1427724.
https://scholarworks.utep.edu/dissertations/AAI1427724