ASIC block level design to physical layout process using diverse CAD tools
Abstract
Block level design to physical layout using Diverse Cad Tools is a process where software applications for ASIC design are combined. Although, the ASIC process is more complicated and expensive than the FPGA process, it offers more levels of customization. In this thesis, the process is not only explained, teaching and learning in conjunction with the use of the tools at levels of at both student and researcher levels are explained. This was achieving through the use of tutorials in form of webpages, making the process more accessible and easy to use. The main objective was to provide future students with enough guidance and information to help in the creation of designs and projects for a given class or a research project.
Subject Area
Electrical engineering|Computer science
Recommended Citation
Perea, Roberto Alfonso, "ASIC block level design to physical layout process using diverse CAD tools" (2004). ETD Collection for University of Texas, El Paso. AAI1423712.
https://scholarworks.utep.edu/dissertations/AAI1423712