Publication Date
2026
Abstract
As high-performance computing becomes progressively heterogeneous, the dependence upon vendor specific tools for numerical correctness has become an impediment to portability. Although modern GPUs comply with the IEEE 754 standard, the lack of practical native hardware support to raise and handle exceptions (special values like ±∞ or NaN) is a well-known architectural limitation. To embed portable numerical correctness across heterogeneous systems, we propose an architecture agnostic prototype based on LLVM-compiler infrastructure. This framework detects floating-point exceptions in GPU kernels at the Intermediate Representation (IR) level, instrumenting both device code and host code, strictly complying with the 2019 IEEE 754 standard. The host side is integrated with a customized PAPIspecific Software-Definedd Events (SDE) based library, exposing the exception events to standard HPC logging and monitoring workflows. Currently implemented for NVIDIA CUDA kernels, this IR- level design can be extended fundamentally to port into GPU backends. Because it classifies exceptions by operation semantics, the tool reports both where exceptional values originate and where they propagate. The tool detects exceptions with a geometric-mean kernel-time overhead of 1.71×. We evaluated it on benchmarks from the Rodinia, PolyBench, SHOC, Parboil, and ECP XSBench proxy, using GPU-FPX as the baseline for comparison