Date of Award
Doctor of Philosophy
Energy harvesting and functional reconfigurability are necessary features in order to simultaneously achieve longer operating lifetimes and versatility in application for many next generation electronic systems. The presented research incorporates capabilities that not only enable applications to self-power from ambience but also permit change in functionality based on real-time application requirements. Currently, many applications are battery powered with custom hardware, which severely confines the application platform. Moreover, maintenance and upgrades are prohibitively expensive, particularly in the case of remote locations with limited accessibility. For harsh environments like Space or the battlefield, apart from features such as low power and econfigurability, robust circuit design is also essential to withstand the effects of radiation and noise. The proposed research implements the Subthreshold Radhard Reconfigurable (SRR) architecture that collectively addresses these three design requirements:
1) radiation hardness with Single Event Upset (SEU) immune circuits,
2) self-powering with subthreshold voltage operation, and
3) functional adaptability with a programmable processing element.
The proposed architecture is a unique solution - well suited for the next generation systems that can simultaneously harvest energy from ambience, reconfigure based on immediate application requirements, and provide robust operation even in harsh environments.
In the course of the SRR design, that combined reconfigurability, subthreshold and robust operation novel subthreshold optimized circuits were proposed and evaluated for the first time.
The proposed circuits include: (1) a Modified Sense Amplifier C2MOS Flip-Flop (MOSAC FF), which enables SEU/SET (Single Event Transient) resilience with 50% reduced power and 20% better SET critical charge (Qcrit) values compared to the best existing design, (2) Body-Tied Level Shifter, which provides 13% increased performance, and (3) Charge Pump, which provides 15% increased output voltage gain at subthreshold voltages when compared to existing designs. These proposed novel circuits, in a design competition sponsored by DARPA, were awarded fabrication at Massachusetts Institute of Technology's Lincoln Laboratory (MITLL), which provides the first ever CMOS technology specifically optimized for subthreshold operation.
The functional verification of the proposed architecture is performed by configuring the design as a 16-bit Multiply Accumulate (MAC) unit using 45nm IBM-12SOI fully depleted transistor model in HSPICE. For comparison purposes, two designs were considered: (1) the Application Specific MAC (ASMAC) design employing adaptive body-bias supply and (2) an off-the-shelf commercial Xilinx Field Programmable Gate Array (FPGA) configured to function as 16-bit MAC. The ASMAC design reported better power consumption values than the proposed design but lacked application flexibility and design robustness. Similarly, in comparison to the proposed design, the commercial FPGA provided application flexibility and substantial performance, at the expense of several orders of increased power consumption. Furthermore, the FPGA implementation lacked radiation hardness and depended on a dedicated
traditional power supply. The proposed architecture was not as power efficient as the ASMAC; however, the slight increase in power is a necessary trade-off when considering the additional features provided, which include robustness, ultra-low power operation, and application
adaptability. Consequently the proposed design is apt for applications requiring self-powering, versatile application, and operation in harsh environments.
Received from ProQuest
Ameet O. Chavan
Chavan, Ameet O., "A Subthreshold Reconfigurable Architecture For Harsh Environments" (2010). Open Access Theses & Dissertations. 1599.