Investigating the Effects of Decoupling Cache and Core Speed on Power, Throughput, and Energy
A variety of computer systems from HPC to mobile systems are power limited and performance sensitive. These systems use very similar components at different scales. Dynamic Voltage and Frequency Scaling (DVFS) features enable modulation of CPU performance and efficiency characteristics to power, energy and timing requirements. Programs have a variety of computational characteristics. If a CPU subsystem substantially limits a particular program’s execution progress, that program’s throughput will vary proportionally with the subsystem’s clock frequency. In contrast, if a CPU subsystem does not substantially limit throughput, the impact of a change in its clock frequency will result in a diminimus change in a program’s execution time. Dynamic Voltage and Frequency Scaling (DVFS) power domains commonly encompass entire cores and their associated caches. This work indicates that moderate energy efficiency gains may be attainable for some programs if limiting and non-limiting subsystems’ (D)VFS domains are decoupled. This decoupling enables tuning of their relative performance to application characteristics. Widely used simulation and modeling tools were extended to support this exploratory research.
Pruitt, David Daniel, "Investigating the Effects of Decoupling Cache and Core Speed on Power, Throughput, and Energy" (2022). ETD Collection for University of Texas, El Paso. AAI29320856.