Design of a low voltage analog to digital converter
For the past 40 years, the number of transistors per chip has been increasing at an exponential rate confirming Moore’s Law regarding the growth of chip complexity. Increases in transistor count have led to enhancements in functionality and made possible products with features that were unimaginable ten years ago. Consequently, the resulting increase in digitization in all electronics, across a wide range of applications, requires the Analog-to-Digital Converters (ADCs) with a higher resolution and lower power consumption. The evolution of the integrated circuit technologies and scaling methodologies partially helps in providing faster circuits and allowing complex functionalities in a given silicon area. The objective of the present work is to better understand the design of ADCs in the context of low voltage operation as a function of temperature, speed and power consumption. However, one requirement in designing faster circuits with transistor of smaller geometries is reducing the supply voltages. Additionally, the increase in the number of battery-operated applications has focused in reducing the supply voltage in current designs to improve energy efficiency. Few low voltage methodologies have been studied and implemented for analog circuits in general and more specifically for ADCs. In the present work, an ADC was designed which implemented the Successive Approximation (SAR) method – based on a binary search. The functionality of ADC was tested in simulation by applying a DC voltage and a ramp signal as the input and analyzing the resulting output digital codes. The power consumption at different temperatures and supply voltages was recorded and analyzed. The results indicate that the effect of temperature on power consumption is significant. The SAR ADC was designed for TSMC 0.25μm CMOS technology. The design of the ADC at the schematic level was captured in Virtuoso Cadence. Cadence offers an integrated Electronic Design Automation (EDA) solution, which encompasses the entire design flow from behavioral modeling to post-layout simulation. The Spectre simulator from Cadence was used to analyze the behavior of the ADC at different voltages and temperatures through simulation. Finally, a built-in Cadence calculator was used to calculate the power consumption and Spurious-free dynamic range (SFDR) at different voltages and temperatures to compare the design to previously reported ADCs. The ADC was simulated at 27°C with the sinusoidal signal as the input. The input sinusoidal signal has 0.5 V P-P running at frequency of 500 Hz. The SFDR and the power consumption for the ADC at these conditions were calculated to be 40.56 dB and 2.5640 μW respectively – a 63% decrease in power consumption in the proposed design relative to the leading ADC reported in literature with 60 times decrease in speed.
Computer Engineering|Electrical engineering
Palakurthi, Praveen Kumar, "Design of a low voltage analog to digital converter" (2009). ETD Collection for University of Texas, El Paso. AAI1473882.