Subthreshold SOI logic for digital integrated circuits
Ultra-low power operation is increasingly becoming more important as the number of battery-power electronics applications continue to grow. Subthreshold CMOS is a recently proposed aggressive design style that trades off performance for lower power consumption---dramatically reducing power by several orders of magnitude. Several design styles have been proposed for this non-traditional operating point and this thesis provides a comprehensive comparison of the advantages and disadvantages of the various styles. Additionally, a standard cell library of combinational and sequential CMOS circuits is constructed to demonstrate the performance and power trade-off associated with subthreshold and superthreshold circuit design.
Graniello, Benjamin Atilio, "Subthreshold SOI logic for digital integrated circuits" (2005). ETD Collection for University of Texas, El Paso. AAI1430261.