A low noise CMOS LC voltage controlled oscillator
In this thesis the design of 2 GHz low noise voltage control oscillator in a standard 0.24-μm CMOS technology is presented. In order to provide low phase noise with optimal tuning range, a negative resistance cross-coupled, fully differential Inductance-Capacitance (LC) tuned voltage control oscillator is implemented. The proposed schematic uses cross-coupled NMOS and PMOS transistors equivalent to the negative resistance compensating the energy loss in the LC tank. The layout of an inductor plays an important role in designing good voltage controlled oscillator. In our design the LC tank uses an inductor of optimal value resulting in an uncomplicated layout of the inductor. Voltage variable capacitors (varactors) were used for obtaining a good tuning range. These were designed as reversed-biased PN junction diodes using Advanced Design System (ADS). An oscillator port provided by ADS tool was used for measuring phase noise characteristics. The circuit was simulated using transient and harmonic balance simulators. The proposed design provides an oscillating frequency of 2GHz at an offset of 100kHz with an optimal phase noise of -104.099 dBc/Hz and tuning range of 6.1% with reasonable quality factor of 4.06 and output power 15dBm. The circuit consumes 1.09mA from a supply voltage of 3.3V. The power consumption of the schematic is 3.59mW.
Konda, Kalyan Chakravarthy, "A low noise CMOS LC voltage controlled oscillator" (2005). ETD Collection for University of Texas, El Paso. AAI1430254.