Publication Date




Published in Proceedings of the ACM Symposium on Applied Computing SAC'06, Dijon, France, April 23-27, 2006, pp. 1645-1649.


In chip design, one of the main objectives is to decrease its clock cycle. On the design stage, this time is usually estimated by using worst-case (interval) techniques, in which we only use the bounds on the parameters that lead to delays. This analysis does not take into account that the probability of the worst-case values is usually very small; thus, the resulting estimates are over-conservative, leading to unnecessary over-design and under-performance of circuits. If we knew the exact probability distributions of the corresponding parameters, then we could use Monte-Carlo simulations (or the corresponding analytical techniques) to get the desired estimates. In practice, however, we only have partial information about the corresponding distributions, and we want to produce estimates that are valid for all distributions which are consistent with this information.

In this paper, we develop a general technique that allows us, in particular, to provide such estimates for the clock time.

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Original file: UTEP-CS-05-31